Computer systems continue to evolve, with ever faster processing speeds, greater data handling capabilities, and increasing storage capacity. Memory buses also handle increased data density with tighter timing requirements (increased sensitivity to delays caused by an amount of time that a memory controller must wait before a next data bit can be passed to the memory bus).
FIG. 1 illustrates an exemplary computer system comprising a central processing unit (CPU) 102 interconnected to a graphics processing unit (GPU) 104, one or more memory modules 106, and a plurality of input/output (I/O) devices 112 through a core logic chipset comprising a Northbridge 108 and a Southbridge 110. As illustrated in FIG. 1, the Northbridge 108 provides a high-speed interconnect between the CPU 102, the GPU 104, and memory modules 106, while the Southbridge 110 provides lower speed interconnections to one or more I/O modules 112. As illustrated in FIG. 1, the interconnection may be implemented with a memory controller 114. Two or more of the CPU 102, GPU 104, Northbridge 108, and Southbridge 110 may be combined in an integrated unit.
One or more graphics cards 104 may be connected to the Northbridge 108 via a high-speed graphics bus (AGP) or a peripheral component interconnect express (PCIe) bus. The one or more memory modules 106 may be connected to the Northbridge 108 via a memory bus. The Northbridge 108 and the Southbridge 110 may be interconnected via an internal bus. Meanwhile, the Southbridge 110 may provide interconnections to a variety of I/O modules 112. The I/O modules 112 may comprise one or more of a PCI bus, serial ports, parallel ports, disc drives, universal serial bus (USB), Ethernet, and peripheral input devices (e.g., keyboard and mouse).
As illustrated in FIG. 2A, a channel 200 of a memory bus may comprise a source node 202 and a destination node 204. For example, the source node 202 may be part of a memory module 106, a memory controller 114, and a memory cache, while the destination node 204 may also be part of the memory module 106 (when the source node 202 is part of the memory controller 114), the memory controller 114 (when the source node 202 is part of the memory module 106 and the memory cache), and the memory cache (when the source node 202 is part of the memory controller 114). As illustrated in FIG. 2B, a memory bus may also comprise a plurality of channels 200a-200n. As also illustrated in FIG. 2B, a memory bus may comprise 512 or 1028 channels 200. A memory bus may also comprise other quantities of channels 200.
Because a finite amount of time is needed for a data sample to propagate from a source node 202 to a destination node 204, a next data sample can't be sent down the memory bus until a current data sample has completed its journey down the memory bus. As illustrated in FIGS. 2A and 2B, when a memory bus channel 200 contains no buffering, the data transmission delay comprises the entire propagation delay required for the current data sample to propagate completely through the memory bus. As illustrated in FIG. 3, one solution is to add a buffer 302 into each of the channels 200 of the memory bus, which can cut the propagation delay in half. As soon as the data sample gets past the added buffer 302, a next data sample can be sent. In other words, the source node 202 doesn't have to wait until a first data sample has travelled along the entire length of the memory bus channel 200 before sending a next data sample. Such a buffer 302 may double the memory bus channel bandwidth. As also illustrated in FIG. 3, the buffer 302 may be a flip flop, which samples data when a rising edge 304 of a clock signal is received.